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A–6 Alpha Instruction Set
21264/EV68A Hardware Reference Manual
Alpha Instruction Summary
LDS Mem 22 Load S_floating
LDT Mem 23 Load T_floating
LDWU Mem 0C Load zero-extended word
MAXSB8 Opr 1C.3E Vector signed byte maximum
MAXSW4 Opr 1C.3F Vector signed word maximum
MAXUB8 Opr 1C.3C Vector unsigned byte maximum
MAXUW4 Opr 1C.3D Vector unsigned word maximum
MB Mfc 18.4000 Memory barrier
MF_FPCR F-P 17.025 Move from FPCR
MINSB8 Opr 1C.38 Vector signed byte minimum
MINSW4 Opr 1C.39 Vector signed word minimum
MINUB8 Opr 1C.3A Vector unsigned byte minimum
MINUW4 Opr 1C.3B Vector unsigned word minimum
MSKBL Opr 12.02 Mask byte low
MSKLH Opr 12.62 Mask longword high
MSKLL Opr 12.22 Mask longword low
MSKQH Opr 12.72 Mask quadword high
MSKQL Opr 12.32 Mask quadword low
MSKWH Opr 12.52 Mask word high
MSKWL Opr 12.12 Mask word low
MT_FPCR F-P 17.024 Move to FPCR
MULF F-P 15.082 Multiply F_floating
MULG F-P 15.0A2 Multiply G_floating
MULL Opr 13.00 Multiply longword
MULL/V Opr 13.40 Multiply longword with integer overflow enable
MULQ Opr 13.20 Multiply quadword
MULQ/V Opr 13.60 Multiply quadword with integer overflow enable
MULS F-P 16.082 Multiply S_floating
MULT F-P 16.0A2 Multiply T_floating
ORNOT Opr 11.28 Logical sum with complement
PERR Opr 1C.31 Pixel error
PKLB Opr 1C.37 Pack longwords to bytes
Table A–2 Architecture Instructions (Continued)
Mnemonic Format Opcode Description