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D–10 PALcode Restrictions and Guidelines
21264/EV68A Hardware Reference Manual
Restriction 9 : PALmode Istream Address Ranges
Bad_interrupt_flow_entry:
ADDQ R31,R31,R0
STF Fa,(Rb) ; This STF might not undergo a dirty source register
; check and might give wrong results
ADDQ R31,R31,R0
ADDQ R31,R31,R0
................................
Good_interrupt_flow_entry:
ADDQ R31,R31,R0; Enables FP dirty source register
; check for (PC[1:0] == 00)
ADDQ R31,R31,R0; Enables FP dirty source register
; check for (PC[1:0] == 01)
ADDQ R31,R31,R0; Enables FP dirty source register
; check for (PC[1:0] == 10)
ADDQ R31,R31,R0; Enables FP dirty source register
; check for (PC[1:0] == 11)
ADDQ R31,R31,R0
STF Fa,(Rb); This STF will successfully undergo
; a dirty source register check
ADDQ R31,R31,R0
ADDQ R31,R31,R0
D.6 Restriction 9 : PALmode Istream Address Ranges
PALmode[physical] Istream addresses must ensure proper sign extension for the
selected value of I_CTL[VA_48]. When I_CTL[VA_48] is clear, indicating 43-bit vir-
tual address format, PALmode[physical] Istream addresses must sign-extend address
bits above bit 42 although the physical address range is 44 bits. An illegal address can
only be generated by a PALmode JSR-type instruction or a HW_RET instruction
returning to a PALmode address.
D.7 Restriction 10: Duplicate IPR Mode Bits
The virtual address size is selectable by programming IPR bits I_CTL[VA_48]
and VA_CTL[VA_48]. These bit values should usually be equal when operating in
native (virtual) mode. The I_CTL[VA_48] bit determines the DTB double3/double4
PALcode entry, the JSR mispredict comparison width, the VPC address generation
width, the Istream ACV limits, and the IVA_FORM format selection. The
VA_CTL[VA_48] bit determines the VA_FORM format selection and the Dstream
ACV limits. IPR mode bits I_CTL[VA_FORM_32] and VA_CTL[VA_FORM_32]
should be consistent when executing in native mode.