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21264/EV68A Hardware Reference Manual
Alpha Instruction Set A–9
IEEE Floating-Point Instructions
A.2.2 Opcodes Reserved for PALcode
Table A–4 lists the 21264/EV68A-specific instructions. See Chapter 2 for more
information.
A.3 IEEE Floating-Point Instructions
Table A–5 lists the hexadecimal value of the 11-bit function code field for the IEEE
floating-point instructions, with and without qualifiers. The opcode for these
instructions is 16
16
.
Table A–4 Opcodes Reserved for PALcode
21264/EV68A
Mnemonic Opcode
Architecture
Mnemonic Function
HW_LD 1B PAL1B Performs Dstream load instructions.
HW_ST 1F PAL1F Performs Dstream store instructions.
HW_REI 1E PAL1E Returns instruction flow to the program counter (PC) pointed
to by EXC_ADDR internal processor register (IPR).
HW_MFPR 19 PAL19 Accesses the Ibox, Mbox, and Dcache IPRs.
HW_MTPR 1D PAL1D Accesses the Ibox, Mbox, and Dcache IPRs.
Table A–5 IEEE Floating-Point Instruction Function Codes
Mnemonic None /C /M /D /U /UC /UM /UD
ADDS
080 000 040 0C0 180 100 140 1C0
ADDT
0A0 020 060 0E0 1A0 120 160 1E0
CMPTEQ
0A5————— — —
CMPTLT
0A6————— — —
CMPTLE
0A7————— — —
CMPTUN
0A4————— — —
CVTQS
0BC 03C 07C 0FC — — — —
CVTQT
0BE 03E 07E 0FE — — — —
CVTST
See
below
————— — —
CVTTQ
See
below
————— — —
CVTTS
0AC 02C 06C 0EC 1AC 12C 16C 1EC
DIVS
083 003 043 0C3 183 103 143 1C3
DIVT
0A3 023 063 0E3 1A3 123 163 1E3
MULS
082 002 042 0C2 182 102 142 1C2
MULT
0A2 022 062 0E2 1A2 122 162 1E2