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Glossary–2
21264/EV68A Hardware Reference Manual
asynchronous system trap (AST)
A software-simulated interrupt to a user-defined routine. ASTs enable a user process to
be notified asynchronously, with respect to that process, of the occurrence of a specific
event. If a user process has defined an AST routine for an event, the system interrupts
the process and executes the AST routine when that event occurs. When the AST rou-
tine exits, the system resumes execution of the process at the point where it was inter-
rupted.
bandwidth
Bandwidth is often used to express the rate of data transfer in a bus or an I/O channel.
barrier transaction
A transaction on the external interface as a result of an MB (memory barrier) instruc-
tion.
Bcache
See second-level cache.
bidirectional
Flowing in two directions. The buses are bidirectional; they carry both input and output
signals.
BiSI
Built-in self-initialization.
BiST
Built-in self-test.
bit
Binary digit. The smallest unit of data in a binary notation system, designated as 0 or 1.
bit time
The total time that a signal conveys a single valid piece of information (specified in ns).
All data and commands are associated with a clock and the receiver’s latch on both the
rise and fall of the clock. Bit times are a multiple of the 21264/EV68A clocks. Systems
must produce a bit time identical to 21264/EV68A’s bit time. The bit time is one-half
the period of the forwarding clock.
BIU
Bus interface unit. See Cbox.
Block exchange
Memory feature that improves bus bandwidth by paralleling a cache victim write-back
with a cache miss fill.
board-level cache
See second-level cache.