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21264/EV68A Hardware Reference Manual
Index–3
Cbox
data register C_DATA
, 5–33
described
, 2–11, 4–3
duplicate Dcache tag array
, 2–11
duplicate Dcache tag array with
, 4–13
HW_MTPR and HW_MFPR to CSR
, D–15
I/O write buffer
, 2–11
internal processor registers
, 5–3
probe queue, 2–11
read register
, 5–41
shift register C_SHFT
, 5–33
victim address file, 2–11
WRITE_MANY chain
, 5–38
WRITE_MANY chain example
, 5–39
WRITE_ONCE chain
, 5–33
CC cycle counter register
, 5–3
at power-on reset state
, 7–15
CC_CTL cycle counter control register
, 5–3
at power-on reset state
, 7–15
CFR_EV6CLK_DELAY Cbox CSR, defined
, 5–38
CFR_FRMCLK_DELAY Cbox CSR, defined
, 5–38
CFR_GCLK_DELAY Cbox CSR, defined
, 5–38
ChangeToDirtyFail, SysDc command
, 4–10, 4–11,
4–12
ChangeToDirtySuccess, SysDc command
, 4–10,
4–11, 4–12
Choice predictor
, 2–5
ChxToDirty, 21264/EV68A command
, 4–12
CLAMP public instruction
, B–1
Clean cache block state
, 4–9
Clean/Shared cache block state
, 4–10
CleanToDirty, 21264/EV68A command
, 4–22,
4–40
system probes, with
, 4–41
CleanVictimBlk, 21264/EV68A command
, 4–22,
4–39
ClkFwdRst_H signal pin
, 3–4, 4–30
with system initialization
, 7–7
ClkIn_x signal pins
, 3–4
Clock forwarding
, 7–4
CLR_MAP clear virtual-to-physical map register
,
5–21
at power-on reset state
, 7–15
CMOV instruction, special cases of
, 2–26
COLD reset machine state
, 7–17
Commands
21264/EV68A to system
, 4–19
system to 21264/EV68A
, 4–26
when to NXM
, 4–38
Conventions
, xix
abbreviations
, xix
address
, xx
aligned
, xx
bit notation
, xx
caution
, xx
data units
, xxi
do not care
, xxi
external, xxi
field notation
, xxi
note
, xxi
numbering, xxi
ranges and extents
, xxi
register figures
, xxi
signal names
, xxi
unaligned
, xx
X
, xxi
CTAG
, 4–13
D
Data cache. See Dcache
Data merging
load instructions in I/O address space
, 2–28
store instructions in I/O address space
, 2–29
Data transfer commands, system
, 4–28
Data types
floating point support
, 1–2
integer supported
, 1–2
supported
, 1–1
Data units convention
, xxi
Data wrap
, 4–36
double-pumped
, 4–38
interleaved, 4–37
DATA_VALID_DLY Cbox CSR, defined
, 5–38
dc
characteristics of
, 9–2
input pin capacitance defined
, 9–2
test load defined
, 9–2
DC_CTL Dcache control register
, 5–30
at power-on reset state
, 7–16
error correction and
, 8–2
DC_PERR error status in C_STAT
, 5–42
DC_STAT Dcache status register
, 5–31
at power-on reset state
, 7–16