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21264/EV68A Hardware Reference Manual
Cache and External Interfaces 4–41
System Port
•
Probes that invalidate locked blocks do not generate a ReadBlkMod command. The
21264/EV68A fails the STx_C instruction as defined in the Alpha Architecture
Handbook, Version 4
.
• All read commands (RdBlk, RdBlkMod, Fetch, InvalToDirty) do not interact
because the 21264/EV68A does not yet own the block.
Table 4–33 21264/EV68A Response to System Probe and In-Flight Command Interaction
Pending Internal
21264/EV68A
Command 21264/EV68A Response to System Probe and In-Flight Command Interaction
ReadBlk
ReadBlkMod
FetchBlk
InvalToDirty
WrVictimBlk
This case assumes that a WrVictimBlk command has been sent to the system and another
agent has performed a load/store instruction to the same address. The 21264/EV68A pro-
vides VAF hit information with the probe response so that the system can manage the race
condition between the WrVictimBlk command from this processor and a possible WrVic-
timBlk command from the probing processor. This race condition can be managed by
either forcing the completion of the WrVictimBlk command to memory before allowing
the progress by the probing processor, or by killing the WrVictimBlk command in this
processor.
CleanToDirty
SharedToDirty
This case assumes that a SetDirty command has been sent to the system environment
because of a store instruction that hit in the 21264/EV68A caches and that another proces-
sor has performed a load/store instruction to the same address. The 21264/EV68A pro-
vides MAF hit information so that the system can correctly respond to the Set/Dirty
command. If the next state of the probe was Invalid (the other processor performed a store
instruction), and the probe reached the system serialization point before the Set/Dirty
command, the system must either fail the Set/Dirty command or provide the updated data
from the other processor.
STCChangeToDirty This case is similar to case 2, except that the initiating instruction for the Set/Dirty com-
mand is a STx_C. An address match with an invalidating probe must fail the Set/Dirty
command. Delivering the updated data from the other processor is not an option because
of the requirements of the LDx_L/STx_C instruction pair.