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21264/EV68A Hardware Reference Manual
PALcode Restrictions and Guidelines D–5
Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
addq r31,r31,r21 /* initialize Shadow Reg. 5*/
br r31, nxt8 /* continue executing in next block*/
tch7: br r31, tch8 /* fetch in next block*/
nxt8: addq r31,r31,r22 /* initialize Shadow Reg. 6*/
addq r31,r31,r23 /* initialize Shadow Reg. 7*/
br r31, nxt9 /* continue executing in next block*/
tch8: br r31, nxt0 /* go back to 1st block and start executing*/
nxt9:
/*
** INIT_WRITE_MANY
**
** Write the cbox write many chain, initializing the bcache configuration.
**
** This code is on a cache block boundary,
**
** *** the bcache is initialized OFF for the burnin test ***
*/
/*
** Because we aligned on and fit into a icache block, and because sbe=0,
** and because we do an mb at the beginning (which blocks further progress
** until the entire block has been fetched in), we don’t have to
** fool with pulling this code in before executing it.
*/
#undef bc_enable_a
#undef init_mode_a
#undef bc_size_a
#undef zeroblk_enable_a
#undef enable_evict_a
#undef set_dirty_enable_a
#undef bc_bank_enable_a
#undef bc_wrt_sts_a
#define bc_enable_a 0
#define init_mode_a 0
#define bc_size_a 0
#define zeroblk_enable_a 1
#define enable_evict_a 0
#define set_dirty_enable_a 0
#define bc_bank_enable_a 0
#define bc_wrt_sts_a 0
loadwm:
lda r1, WRITE_MANY_CHAIN_H(r31)
sll r1, 32, r1 /* data<35:32> */
LDLI(r1, WRITE_MANY_CHAIN_L, r1) /* data<31:00> */
addq r31,6,r0 /* shift in 6x 6-bits*/
mb /* wait for all istream/dstream to complete*/
br r31, bccshf
.align 6
bccshf:mtpr r1,EV6__DATA /* shift in 6 bits*/
subq r0,1,r0 /* decrement R0*/
beq r0,bccend /* done if R0 is zero*/
srl r1,6,r1 /* align next 6 bits*/