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4–38 Cache and External Interfaces
21264/EV68A Hardware Reference Manual
System Port
Table 4–31 defines the wrap order for double-pumped data transfers.
4.7.9 Nonexistent Memory Processing
Like its predecessors, the 21264/EV68A can generate references to nonexistent (NXM)
memory or I/O space. However, unlike the earlier Alpha microprocessor implementa-
tions, the 21264/EV68A can generate speculative references to memory space. To
accommodate the speculative nature of the 21264/EV68A, the system must not gener-
ate or lock error registers because of speculative references. The 21264/EV68A trans-
lates all memory references through the translation lookaside buffer (TLB) and, in some
cases, the 21264/EV68A may generate speculative references (instruction execution
down mispredicted paths) to NXM space. In these cases, the system sends a SysDc
ReadDataError and the 21264/EV68A does the following:
• Delivers an all-ones pattern to all load instructions to the NXM address
• Force-fails all store instructions to the NXM address (much like a STx_C
failure)
• Invalidates the cache block at the same index by way of an atomic Evict
command
Sixth quadword 101 111 001 011
Seventh quadword 110 100 010 000
Eighth quadword 111 101 011 001
Table 4–31 Wrap Order for Double-Pumped Data Transfers
PA[5:3]ofTransferredQW
First quadword x00 x01 x10 x11
Second quadword x00 x01 x10 x11
Third quadword x01 x00 x11 x10
Fourth quadword x01 x00 x11 x10
Fifth quadword x10 x11 x00 x01
Sixth quadword x10 x11 x00 x01
Seventh quadword x11 x10 x01 x00
Eighth quadword x11 x10 x01 x00
Table 4–30 Wrap Interleave Order (Continued)
PA Bits [5:3] of Transferred QW