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21264/EV68A Hardware Reference Manual
Internal Architecture 2–21
Instruction Retire Rules
2.4 Instruction Retire Rules
An instruction is retired when it has been executed to completion, and all previous
instructions have been retired. The execution pipeline stage in which an instruction
becomes eligible to be retired depends upon the instruction’s class.
Table 2–5 gives the minimum retire latencies (assuming that all previous instructions
have been retired) for various classes of instructions.
fadd 4
6
Consumer other than fst or ftoi.
Consumer fst or ftoi.
Measured from when an fadd is issued from the FQ to when an fst or ftoi is issued
from the IQ.
fmul 4
6
Consumer other than fst or ftoi.
Consumer fst or ftoi.
Measured from when an fmul is issued from the FQ to when an fst or ftoi is issued
from the IQ.
fcmov1 4 Only consumer is fcmov2.
fcmov2 4
6
Consumer other than fst.
Consumer fst or ftoi.
Measured from when an fcmov2 is issued from the FQ to when an fst or ftoi is
issued from the IQ.
fdiv 12
9
15
12
Single precision - latency to consumer of result value.
Single precision - latency to using divider again.
Double precision - latency to consumer of result value.
Double precision - latency to using divider again.
fsqrt 18
15
33
30
Single precision - latency to consumer of result value.
Single precision - latency to using unit again.
Double precision - latency to consumer of result value.
Double precision - latency to using unit again.
ftoi 3 —
itof 4 —
nop — Does not produce register value.
Table 2–5 Minimum Retire Latencies for Instruction Classes
Instruction Class Retire Stage Comments
Integer conditional branch 7 —
Integer multiply 7/13 Latency is 13 cycles for the MUL/V instruction.
Integer operate 7 —
Memory 10 —
Floating-point add 11 —
Floating-point multiply 11 —
Table 2–4 Instruction Class Latency in Cycles (Continued)
Class Latency Comments