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Glossary–4
21264/EV68A Hardware Reference Manual
cache hit
The status returned when a logic unit probes a cache memory and finds a valid cache
entry at the probed address.
cache interference
The result of an operation that adversely affects the mechanisms and procedures used to
keep frequently used items in a cache. Such interference may cause frequently used
items to be removed from a cache or incur significant overhead operations to ensure
correct results. Either action hampers performance.
cache line
See cache block.
cache line buffer
A buffer used to store a block of cache memory.
cache memory
A small, high-speed memory placed between slower main memory and the processor. A
cache increases effective memory transfer rates and processor speed. It contains copies
of data recently used by the processor and fetches several bytes of data from memory in
anticipation that the processor will access the next sequential series of bytes. The
21264/EV68A microprocessor contains two onchip internal caches. See also write-
through cache and write-back cache.
cache miss
The status returned when cache memory is probed with no valid cache entry at the
probed address.
CALL_PAL instructions
Special instructions used to invoke PALcode.
Cbox
External cache and system interface unit. Controls the Bcache and the system ports.
central processing unit (CPU)
The unit of the computer that is responsible for interpreting and executing instructions.
CISC
Complex instruction set computing. An instruction set that consists of a large number
of complex instructions. Contrast with RISC.
clean
In the cache of a system bus node, refers to a cache line that is valid but has not been
written.
clock
A signal used to synchronize the circuits in a computer.