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21264/EV68A Hardware Reference Manual
Introduction 1–1
1
Introduction
This chapter provides a brief introduction to the Alpha architecture, Compaq’s RISC
(reduced instruction set computing) architecture designed for high performance. The
chapter then summarizes the specific features of the Alpha 21264/EV68A microproces-
sor (hereafter called the 21264/EV68A) that implements the Alpha architecture. Appen-
dix A provides a list of Alpha instructions.
The companion volume to this document, the Alpha Architecture Reference Manual,
Fourth Edition, contains the complete architecture information.
1.1 The Architecture
The Alpha architecture is a 64-bit load and store RISC architecture designed with par-
ticular emphasis on speed, multiple instruction issue, multiple processors, and software
migration from many operating systems.
All registers are 64 bits long and all operations are performed between 64-bit registers.
All instructions are 32 bits long. Memory operations are either load or store operations.
All data manipulation is done between registers.
The Alpha architecture supports the following data types:
• 8-, 16-, 32-, and 64-bit integers
• IEEE 32-bit and 64-bit floating-point formats
• VAX architecture 32-bit and 64-bit floating-point formats
In the Alpha architecture, instructions interact with each other only by one instruction
writing to a register or memory location and another instruction reading from that regis-
ter or memory location. This use of resources makes it easy to build implementations
that issue multiple instructions every CPU cycle.
The 21264/EV68A uses a set of subroutines, called privileged architecture library code
(PALcode), that is specific to a particular Alpha operating system implementation and
hardware platform. These subroutines provide operating system primitives for context
switching, interrupts, exceptions, and memory management. These subroutines can be
invoked by hardware or CALL_PAL instructions. CALL_PAL instructions use the
function field of the instruction to vector to a specified subroutine. PALcode is written
in standard machine code with some implementation-specific extensions to provide
direct access to low-level hardware functions. PALcode supports optimizations for mul-
tiple operating systems, flexible memory-management implementations, and multi-
instruction atomic sequences.