Filter
Top Products
5–34 Internal Processor Registers
21264/EV68A Hardware Reference Manual
Cbox CSRs and IPRs
•
Only a brief description of each CSR is given. The functional description of these
CSRs is contained in Chapter 4.
• The order of multibit vectors is [MSB:LSB], so the LSB is first bit in the Cbox
chain.
Table 5–24 describes the Cbox WRITE_ONCE chain order from LSB to MSB.
Table 5–24 Cbox WRITE_ONCE Chain Order
Cbox WRITE_ONCE Chain Description
32_BYTE_IO[0] Enable 32_BYTE I/O mode.
BC_CLK_RATIO[1] Asserted when Bcache is at 1.5x ratio.
SKEWED_FILL_MODE[0] Must be asserted for Bcache 1.5x ratio; for maximum performance,
canalsobeassertedfor3.0xand3.5xratios.
DCVIC_THRESHOLD[7:0] Threshold of the number of Dcache victims that will accumulate
before streamed write transactions to the Bcache are initiated. The
Cbox can accumulate up to six victims for streamed Dcache pro-
cessing. This register is programmed with the decoded value of the
threshold count.
BC_CLEAN_VICTIM[0] Enable clean victims to the system interface.
SYS_BUS_SIZE[1:0] Size of SysAddOut and SysAddOut buses.
SYS_BUS_FORMAT[0] Indicates system bus format.
SYS_CLK_RATIO[4:1] Speed of system bus.
Code Multiplier
0001 1.5X
0010 2.0X
0100 2.5X
1000 3.0X
DUP_TAG_ENABLE[0] Enable duplicate tag mode in the 21264/EV68A.
PRB_TAG_ONLY[0] Enable probe-tag only mode in the 21264/EV68A.
FAST_MODE_DISABLE[0] When asserted, disables fast data movement mode.
BC_RDVICTIM[0] Enables RdVictim mode on the pins.
BC_CLEAN_VICTIM[0] Duplicate CSR.
RDVIC_ACK_INHIBIT Enable inhibition of incrementing acknowledge counter for RdVic
commands.
SYSBUS_MB_ENABLE Enable MB commands offchip.
SYSBUS_ACK_LIMIT[0:4] Sysbus acknowledge limit CSR.
SYSBUS_VIC_LIMIT[0:2] Limit for victims.
BC_CLEAN_VICTIM[0] Duplicate CSR.
BC_WR_WR_BUBBLE[0] Write to write GCLK bubble.
BC_RD_WR_BUBBLES[0:5] Read to write GCLK bubbles for the Bcache interface.
BC_RD_RD_BUBBLE[0] Read to read GCLK bubble for banked Bcaches.
BC_SJ_BANK_ENABLE Enable bank mode for Bcache.