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4–18 Cache and External Interfaces
21264/EV68A Hardware Reference Manual
System Port
4.7.2 Programming the System Interface Clocks
The system forwarded clocks are free running and derived from the 21264/EV68A
GCLK. The period of the system forwarded clocks is controlled by three Cbox CSRs,
based on the bit-rate ratio (similar to the Bcache bit-rate ratio) except that all transfers
are dual-data.
• SYS_CLK_LD_VECTOR[15:0]
• SYS_BPHASE_LD_VECTOR[3:0]
• SYS_FDBK_EN[7:0]
Table 4–7 lists the programming values used to program the system interface clocks.
In addition to programming of the clock CSRs, the data-sample/drive Cbox CSRs at the
pads have to be set appropriately. Table 4–8 shows the programmed values for these
system CSRs. In Table 4–8, each system forwarded clock is the inversion of the low-
assertion signal at the corresponding pin.
Table 4–7 Programming Values for System Interface Clocks
System Transfer SYS_CLK_LD_VECTOR
1
1
These are hexadecimal values.
SYS_BPHASE_LD_VECTOR
1
SYS_FDBK_EN
1
1.5X-DD 9249 5 02
2.0X-DD 3333 0 01
2.5X-DD 8C63 5 02
3.0X-DD 71C7 0 10
3.5X-DD C387 A 04
4.0X-DD 0F0F 0 01
5.0X-DD 7C1F 0 40
6.0X-DD F03F 0 10
7.0X-DD C07F 0 04
8.0X-DD 00FF 0 01
Table 4–8 Program Values for Data-Sample/Drive CSRs
CBOX CSR Description
SYS_DDM_FALL_EN[0] Enables the update of 21264/EV68A system outputs based on the falling edge
of the system forwarded clock. (Always asserted)
SYS_DDM_RISE_EN[0] Enables the update of 21264/EV68A system outputs based on the rising edge
of the system forwarded clock. (Always asserted)
SYS_DDM_RD_FALL_EN[0] Enables the sampling of incoming data on the falling edge of the incoming
forwarded clock. (Always asserted)