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21264/EV68A Hardware Reference Manual
interface reset
A synchronously received reset signal that is used to preset and start the clock forward-
ing circuitry. During this reset, all forwarded clocks are stopped and the presettable
count values are applied to the counters; then, some number of cycles later, the clocks
are enabled and are free running.
Internal processor register (IPR)
Special registers that are used to configure options or report status.
IOWB
I/O write buffer.
IPGA
Interstitial pin grid array.
IQ
Integer issue queue.
ITB
Instruction translation buffer.
JFET
Junction field-effect transistor.
latency
The amount of time it takes the system to respond to an event.
LCC
Leadless chip carrier.
LFSR
Linear feedback shift register.
load/store architecture
A characteristic of a machine architecture where data items are first loaded into a pro-
cessor register, operated on, and then stored back to memory. No operations on memory
other than load and store are provided by the instruction set.
longword (LW)
Four contiguous bytes starting on an arbitrary byte boundary. The bits are numbered
from right to left, 0 through 31.
LQ
Load queue.
LSB
Least significant bit.