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A–14 Alpha Instruction Set
21264/EV68A Hardware Reference Manual
IEEE Floating-Point Conformance
A.8 IEEE Floating-Point Conformance
The 21264/EV68A supports the IEEE floating-point operations defined in the Alpha
System Reference Manual, Revision 8 and therefore also from the Alpha Architecture
Reference Manual, Fourth Edition. Support for a complete implementation of the IEEE
Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754 1985) is pro-
vided by a combination of hardware and software. The 21264/EV68A provides several
hardware features to facilitate complete support of the IEEE standard.
The 21264/EV68A provides the following hardware features to facilitate complete sup-
port of the IEEE standard:
• The 21264/EV68A implements precise exception handling in hardware, as denoted
by the AMASK instruction returning bit 9 set. TRAPB instructions are treated as
NOPs and are not issued.
• The 21264/EV68A accepts both Signaling and Quiet NaNs as input operands and
propagates them as specified by the Alpha architecture. In addition, the 21264/
EV68A delivers a canonical Quiet NaN when an operation is required to produce a
NaN value and none of its inputs are NaNs. Encodings for Signaling NaN and
Quiet NaN are defined by the Alpha Architecture Reference Manual, Fourth Edi-
tion.
• The 21264/EV68A accepts infinity operands and implements infinity arithmetic as
defined by the IEEE standard and the Alpha Architecture Reference Manual,
Fourth Edition.
• The 21264/EV68A implements SQRT for single (SQRTS) and double (SQRTT)
precision in hardware.
Note: In addition, the 21264/EV68A also implements the VAX SQRTF and
SQRTG instructions.
• The 21264/EV68A implements the FPCR[DNZ] bit. When FPCR[DNZ] is set,
denormal input operand traps can be avoided for arithmetic operations that include
the /S qualifier. When FPCR[DNZ] is clear, denormal input operands for arithmetic
operations produce an unmaskable denormal trap. CPYSE/CPYSN, FCMOVxx,
and MF_FPCR/MT_FPCR are not arithmetic operations, and pass denormal values
without initiating arithmetic traps.
• The 21264/EV68A implements the following disable bits in the floating-point con-
trol register (FPCR):
– Underflow disable (UNFD)
– Overflow disable (OVFD)
– Inexact result disable (INED)
– Division by zero disable (DZED)
– Invalid operation disable (INVD)