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21264/EV68A Hardware Reference Manual
Internal Processor Registers 5–29
Mbox IPRs
Note: The Ra field of the instruction that triggered the error can be obtained from
the Ibox EXC_SUM register.
5.3.9 Mbox Control Register – M_CTL
The Mbox control register (M_CTL) is a write-only register. Its contents are cleared by
chip reset. Figure 5–32 shows the Mbox control register.
Figure 5–32 Mbox Control Register
FOR [2] RO This bit is set when a fault-on-read error occurs during a read
transaction and PTE[FOR] was set.
ACV [1] RO This bit is set when an access violation occurs during a transac-
tion. Access violations include a bad virtual address.
WR [0] RO This bit is set when an error occurs during a write transaction.
Table 5–18 Memory Management Status Register Fields Description (Continued)
Name Extent Type Description
63 645310
SMC[1:0]
SPE[2:0]
LK
99
-
00
4
0
A