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21264/EV68A Hardware Reference Manual
Internal Processor Registers 5–11
Ibox IPRs
Figure 5–17 Software Interrupt Request Register
Table 5–6 describes the software interrupt request register fields.
5.2.11 Interrupt Summary Register – ISUM
The interrupt summary register (ISUM) is a read-only register that records all pending
hardware, software, and AST interrupt requests that have their corresponding enable bit
set.
If a new interrupt (hardware, serial line, crd, or performance counters) occurs simulta-
neously with an ISUM read, the ISUM read returns zeros. That condition is normally
assumed to be a passive release condition. The interrupt is signaled again when the
PALcode returns to native mode. The effects of this condition can be minimized by
reading ISUM twice and ORing the results.
Usage of ISUM in performance monitoring is described in Section 6.10. Figure 5–18
shows the interrupt summary register.
Figure 5–18 Interrupt Summary Register
Table 5–6 Software Interrupt Request Register Fields Description
Name Extent Type Description
Reserved [63:29] — —
SIR[15:1] [28:14] RW Software Interrupt Requests
Reserved [13:0] — —
63 2928 1413 0
SIR[15:1]
LK99-0023A
63 39 29 938 28 8 514 433 13 332 231 11 10 0
EI[5:0]
SL
CR
PC[1:0]
SI[15:1]
ASTU
ASTS
ASTE
ASTK
LK
99
-
00
24A
30