Filter
Top Products
21264/EV68A Hardware Reference Manual
PALcode Restrictions and Guidelines D–3
Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
addq r31,r31,r27 /* initialize Int. Reg. 27*/
addt f31,f31,f26 /* initialize F.P. Reg. 26*/
mult f31,f31,f27 /* initialize F.P. Reg. 27*/
addq r31,r31,r28 /* initialize Int. Reg. 28*/
addq r31,r31,r29 /* initialize Int. Reg. 29*/
addt f31,f31,f28 /* initialize F.P. Reg. 28*/
mult f31,f31,f29 /* initialize F.P. Reg. 29*/
addq r31,r31,r30 /* initialize Int. Reg. 30*/
addt f31,f31,f30 /* initialize F.P. Reg. 30*/
addq r31,r31,r0 /* initialize retirator 63*/
addq r31,r31,r0 /* initialize retirator 64*/
addq r31,r31,r0 /* initialize retirator 65*/
addq r31,r31,r0 /* initialize retirator 66*/
addq r31,r31,r0 /* initialize retirator 67*/
addq r31,r31,r0 /* initialize retirator 68*/
addq r31,r31,r0 /* initialize retirator 69*/
addq r31,r31,r0 /* initialize retirator 70*/
addq r31,r31,r0 /* initialize retirator 71*/
addq r31,r31,r0 /* initialize retirator 72*/
addq r31,r31,r0 /* initialize retirator 73*/
addq r31,r31,r0 /* initialize retirator 74*/
addq r31,r31,r0 /* initialize retirator 75*/
addq r31,r31,r0 /* initialize retirator 76*/
addq r31,r31,r0 /* initialize retirator 77*/
addq r31,r31,r0 /* initialize retirator 78*/
addq r31,r31,r0 /* initialize retirator 79*/
addq r31,r31,r0 /* initialize retirator 80*/
/* stop deleting*/
mtpr r31,EV6__ITB_IA /* flush the ITB (SCRBRD=4) *** this also
turns on mapper source enables ****/
mtpr r31,EV6__DTB_IA /* flush the DTB (SCRBRD=7)*/
mtpr r31,EV6__VA_CTL /* clear VA_CTL (SCRBRD=5)*/
mtpr r31,EV6__M_CTL /* clear M_CTL (SCRBRD=6)*/
/*
** Create a stall outside the IQ until the mtpr EV6__ITB_IA retires.
** We can use DTB_ASNx even though we don’t seem to follow the restriction on
** scoreboard bits (4-7).It’s okay because there are no real dstream
** operations happening.
*/
mtpr r31,EV6__DTB_ASN0 /* clear DTB_ASN0 (SCRBRD=4) creates a map-
stall under the above mtpr to SCRBRD=4*/
mtpr r31,EV6__DTB_ASN1 /* clear DTB_ASN1 (SCRBRD=7)*/
mtpr r31,EV6__CC_CTL /* clear CC_CTL (SCRBRD=5)*/
mtpr r31,EV6__DTB_ALT_MODE/* clear DTB_ALT_MODE (SCRBRD=6)*/
/*
** MAP_SHADOW_REGISTERS
**
** The shadow registers are mapped. This code may be done by the SROM