Filter
Top Products
21264/EV68A Hardware Reference Manual
Internal Architecture 2–1
2
Internal Architecture
This chapter provides both an overview of the 21264/EV68A microarchitecture and a sys-
tem designer’s view of the 21264/EV68A implementation of the Alpha architecture. The
combination of the 21264/EV68A microarchitecture and privileged architecture library
code (PALcode) defines the chip’s implementation of the Alpha architecture. If a certain
piece of hardware seems to be “architecturally incomplete,” the missing functionality is
implemented in PALcode. Chapter 6 provides more information on PALcode.
This chapter describes the major functional hardware units and is not intended to be a
detailed hardware description of the chip. It is organized as follows:
• 21264/EV68A microarchitecture
• Pipeline organization
• Instruction issue and retire rules
• Load instructions to R31/F31 (software-directed instruction prefetch)
• Special cases of Alpha instruction execution
• Memory and I/O address space
• Miss address file (MAF) and load-merging rules
• Instruction ordering
• Replay traps
• I/O write buffer and the WMB instruction
• Performance measurement support
• Floating-point control register
• AMASK and IMPLVER instruction values
• Design examples
2.1 21264/EV68A Microarchitecture
The 21264/EV68A microprocessor is a high-performance third-generation implementa-
tion of the Compaq Alpha architecture. The 21264/EV68A consists of the following
sections, as shown in Figure 2–1:
• Instruction fetch, issue, and retire unit (Ibox)
• Integer execution unit (Ebox)