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21264/EV68A Hardware Reference Manual
vii
6.5.3 HardwareStructureofImplicitlyWrittenIPRs ................................ 6–9
6.5.4 IPRAccessOrdering................................................... 6–9
6.5.5 CorrectOrderingofExplicitWritersFollowedbyImplicitReaders................. 6–10
6.5.6 CorrectOrderingofExplicitReadersFollowedbyImplicitWriters................. 6–11
6.6 PALshadow Registers...................................................... 6–11
6.7 PALcodeEmulationoftheFPCR ............................................. 6–11
6.7.1 StatusFlags.......................................................... 6–12
6.7.2 MF_FPCR ........................................................... 6–12
6.7.3 MT_FPCR ........................................................... 6–12
6.8 PALcodeEntryPoints...................................................... 6–12
6.8.1 CALL_PALEntryPoints................................................. 6–12
6.8.2 PALcodeExceptionEntryPoints.......................................... 6–13
6.9 TranslationBuffer(TB)FillFlows............................................. 6–14
6.9.1 DTBFill ............................................................. 6–14
6.9.2 ITBFill.............................................................. 6–16
6.10 Performance Counter Support . . . ............................................ 6–17
6.10.1 GeneralPrecautions ................................................... 6–18
6.10.2 AggregateModeProgrammingGuidelines .................................. 6–18
6.10.2.1 AggregateModePrecautions......................................... 6–18
6.10.2.2 Operation ........................................................ 6–19
6.10.2.3 AggregateCountingModeDescription.................................. 6–20
6.10.2.3.1 Cyclecounting................................................. 6–20
6.10.2.3.2 Retiredinstructionscycles........................................ 6–20
6.10.2.3.3 Bcachemissorlonglatencyprobescycles........................... 6–20
6.10.2.3.4 Mboxreplaytrapscycles......................................... 6–20
6.10.2.4 Counter Modes for Aggregate Mode. . . ................................. 6–20
6.10.3 ProfileMeModeProgrammingGuidelines................................... 6–20
6.10.3.1 ProfileMeModePrecautions.......................................... 6–20
6.10.3.2 Operation ........................................................ 6–21
6.10.3.3 ProfileMe Counting Mode Description . ................................. 6–23
6.10.3.3.1 Cyclecounting................................................. 6–23
6.10.3.3.2 Inumretiredelaycycles.......................................... 6–23
6.10.3.3.3 Retiredinstructionscycles........................................ 6–23
6.10.3.3.4 Bcachemissorlonglatencyprobescycles........................... 6–23
6.10.3.3.5 Mboxreplaytrapscycles......................................... 6–23
6.10.3.4 CounterModesforProfileMeMode.................................... 6–24
7 Initialization and Configuration
7.1 Power-UpResetFlowandtheReset_LandDCOK_HPins......................... 7–1
7.1.1 Power Sequencing and Reset State for Signal Pins ........................... 7–3
7.1.2 ClockForwardingandSystemClockRatioConfiguration....................... 7–4
7.1.3 PLLRampUp......................................................... 7–6
7.1.4 BiSTandSROMLoadandtheTestStat_HPin............................... 7–6
7.1.5 ClockForwardResetandSystemInterfaceInitialization........................ 7–7
7.2 FaultResetFlow.......................................................... 7–8
7.3 EnergyStarCertificationandSleepModeFlow.................................. 7–9
7.4 WarmResetFlow......................................................... 7–11
7.5 ArrayInitialization ......................................................... 7–12
7.6 InitializationModeProcessing................................................ 7–12
7.7 ExternalInterfaceInitialization ............................................... 7–14
7.8 InternalProcessorRegisterPower-UpResetState ............................... 7–14
7.9 IEEE1149.1TestPortReset................................................ 7–16
7.10 ResetStateMachine....................................................... 7–16
7.11 Phase-LockLoop(PLL)FunctionalDescription .................................. 7–19
7.11.1 DifferentialReferenceClocks............................................. 7–19
7.11.2 PLLOutputClocks..................................................... 7–19