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21264/EV68A Hardware Reference Manual
PALcode Restrictions and Guidelines D–23
Restriction 47: Cache Eviction for Single-Bit Cache Errors
If "CBOX_ERR[C_ADDR]" has not changed when the CRD_HANDLER is re-
entered, or "CBOX_ERR[C_STAT] == 0x0", all cache locations should to be evicted to
avoid the live lock described above.
; Sample code for evicting cache.
; This method loads a 64K block, then exits the CRD_HANDLER
; to check if the sberr has been evicted. If not it loads the next 64K block.
; In the sample code below,
; sx is a shadow register
; ldi is a macro that loads a 64-bit constant into the specified register
full_scrub:
hw_ldq/p s5, 104(r31)
ldi s1, ^x200 ; Loop dec value
ldi s2, ^x1C0 ; Start offset
ldi s3, ^x10000 ; Block size (64K -> size of dcache)
ldi s4, ^x2000000 ; 2X bcache size
addq s3,s5,s5
ble s5, s4, <.+4> ; Skip next instruction if ADDR
; .le. 2X bcache
bis r31, r31, s5 ; Set ADDR = 0x0
hw_stq/p s5, 104(r31) ; Store ADDR for next pass thru
subq s5, s2, s5
mb ; Make sure no speculative loads
; happen in the CRD handler
.align 4, NOP_OPCODE ;|
blbc r31, <.+4> ;|
br r31, <.-4> ;V
.align 4, NOP_OPCODE ; Make sure no speculative loads
; happen in the CRD handler
next_reread:
; ******** four cache blocks
; Evict dcache by prefetching to all dcache indexes.
; use 'hw_ldl r31 xxxx' Normal Prefetch
; Do not use 'hw_ldq/p r31 xxx' Prefetch,
; Evict Next because this will always access the same set in dcache.
hw_ldl/p r31,^x1C0(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^x180(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^x140(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^x100(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^xC0(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^x80(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^x40(s5) ; Re-read the bad block QW #0
hw_ldl/p r31,^x00(s5) ; Re-read the bad block QW #0
subq s5, s1, s5 ; Decrement addr
subq s3, s1, s3 ; Decrement counter
ble s3, <.+4>
br r31, next_reread
bsr s7, sys__cbox ; Read and clean cbox error ipr