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2–20 Internal Architecture
21264/EV68A Hardware Reference Manual
Instruction Issue Rules
2.3.3 Instruction Latencies
After an instruction is placed in the IQ or FQ, its issue point is determined by the avail-
ability of its register operands, functional unit(s), and relationship to other instructions
in the queue. There are register producer-consumer dependencies and dynamic func-
tional unit availability dependencies that affect instruction issue. The mapper removes
register producer-producer dependencies.
The latency to produce a register result is generally fixed. The one exception is for load
instructions that miss the Dcache. Table 2–4 lists the latency, in cycles, for each
instruction class.
Table 2–4 Instruction Class Latency in Cycles
Class Latency Comments
ild 3
13+
Dcache hit.
Dcache miss, latency with 6-cycle Bcache. Add additional Bcache loop latency if
Bcache latency is greater than 6 cycles.
fld 4
14+
Dcache hit.
Dcache miss, latency with 6-cycle Bcache. Add additional Bcache loop latency if
Bcache latency is greater than 6 cycles.
lda 1 Possible 1-cycle Ebox cross-cluster delay.
mem_misc — Does not produce register value.
ist — Does not produce register value.
fst — Does not produce register value.
rpcc 1 Possible 1-cycle cross-cluster delay.
rx 1 —
mxpr 1 or 3 HW_MFPR: Ebox IPRs = 1.
Ibox and Mbox IPRs = 3.
HW_MTPR does not produce a register value.
icbr — Conditional branch. Does not produce register value.
ubr 3 Unconditional branch. Does not produce register value.
jsr 3 —
iadd 1 Possible 1-cycle Ebox cross-cluster delay.
ilog 1 Possible 1-cycle Ebox cross-cluster delay.
ishf 1 Possible 1-cycle Ebox cross-cluster delay.
cmov1 1 Only consumer is cmov2. Possible 1-cycle Ebox cross-cluster delay.
cmov2 1 Possible 1-cycle Ebox cross-cluster delay.
imul 7 Possible 1-cycle Ebox cross-cluster delay.
imisc 3 Possible 1-cycle Ebox cross-cluster delay.
fcbr — Does not produce register value.