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21264/EV68A Hardware Reference Manual
Internal Architecture 2–37
AMASK and IMPLVER Instruction Values
2.15 AMASK and IMPLVER Instruction Values
The AMASK and IMPLVER instructions return the supported architecture extensions
and processor type , respectively.
DYN [59:58] RW Dynamic rounding mode. Indicates the rounding mode to be used by an IEEE
floating-point instruction when the instruction specifies dynamic rounding
mode:
IOV [57] RW Integer overflow. A CVTGQ, CVTTQ, or CVTQL overflowed the destination
precision.
INE [56] RW Inexact result. A floating-point arithmetic or conversion operation gave a result
that differed from the mathematically exact result.
UNF [55] RW Underflow. A floating-point arithmetic or conversion operation gave a result
that underflowed the destination exponent.
OVF [54] RW Overflow. A floating-point arithmetic or conversion operation gave a result that
overflowed the destination exponent.
DZE [53] RW Divide by zero. An attempt was made to perform a floating-point divide with a
divisor of zero.
INV [52] RW Invalid operation. An attempt was made to perform a floating-point arithmetic
operation and one or more of its operand values were illegal.
OVFD [51] RW Overflow disable. If this bit is set and a floating-point arithmetic operation gen-
erates an overflow condition, then the appropriate IEEE nontrapping result is
placed in the destination register and the trap is suppressed.
DZED [50] RW Division by zero disable. If this bit is set and a floating-point divide by zero is
detected, the appropriate IEEE nontrapping result is placed in the destination
register and the trap is suppressed.
INVD [49] RW Invalid operation disable. If this bit is set and a floating-point operate generates
an invalid operation condition and 21264/EV68A is capable of producing the
correct IEEE nontrapping result, that result is placed in the destination register
and the trap is suppressed.
DNZ [48] RW Denormal operands to zero. If this bit is set, treat all Denormal operands as a
signed zero value with the same sign as the Denormal operand.
Reserved [47:0]
1
——
1
Alpha architecture FPCR bit 47 (DNOD) is not implemented by the 21264/EV68A.
Table 2–14 Floating-Point Control Register Fields (Continued)
Name Extent Type Description
Bits Meaning
00 Chopped
01 Minus infinity
10 Normal
11 Plus infinity