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4–54 Cache and External Interfaces
21264/EV68A Hardware Reference Manual
Interrupts
BC_CPU_LATE_WRITE_NUM[1:0] = 0x1
BC_LATE_WRITE_NUM[2:0] = 0x0
BC_LATE_WRITE_UPPER = 0
DUP_TAG_ENABLE = 0
4.9 Interrupts
The system may request interrupts by way of the IRQ_H[5:0] pins. These six interrupt
sources are identical. They may be asynchronous, are level sensitive, and can be indi-
vidually masked by way of the EIE field of the CM_IER IPR. The system designer
determines how these signals are used and selects their relative priority.