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21264/EV68A Hardware Reference Manual
Initialization and Configuration 7–15
Internal Processor Register Power-Up Reset State
ITB_IAP ITB invalidate-all (ASM=0) X —
ITB_IA ITB invalidate all X Must be written to in PALcode.
ITB_IS ITB invalidate single X —
PMPC ProfileMePC X —
EXC_ADDR Exception address X —
IVA_FORM Instruction VA format X —
IER_CM Interrupt enable current mode X Must be written to in PALcode.
SIRR Software interrupt request X —
ISUM Interrupt summary X —
HW_INT_CLR Hardware interrupt clear X Must be cleared in PALcode.
EXC_SUM Exception summary X —
PAL_BASE PAL base address Cleared —
I_CTL Ibox control IC_EN = 3 All other bits are cleared on reset.
I_STAT Ibox status X Must be cleared in PALcode.
IC_FLUSH Icache flush X —
CLR_MAP Clear virtual-to-physical map X —
SLEEP Sleep mode X —
PCTX Ibox process context PCTX[FPE] is set. All other bits are X.
PCTR_CTL Performance counter control X Must be cleared in PALcode.
Ebox IPRs
CC Cycle counter X Must be cleared in PALcode.
CC_CTL Cycle counter control X Must be cleared in PALcode.
VA Virtual address X —
VA_FORM Virtual address format X —
VA_CTL Virtual address control X Must be cleared in PALcode.
Mbox IPRs
DTB_TAG0 DTB tag array write 0 Cleared —
DTB_TAG1 DTB tag array write 1 Cleared —
DTB_PTE0 DTB PTE array write 0 Cleared —
DTB_PTE1 DTB PTE array write 1 Cleared —
DTB_ALTMODE DTB alternate processor mode X PALcode must initialize.
DTB_IAP DTB invalidate all process
ASM = 0
X—
DTB_IA DTB invalidate all process X Must be written to in PALcode.
Table 7–10 Internal Processor Registers at Power-Up Reset State (Continued)
Mnemonic Register Name Reset State Comments