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D–16 PALcode Restrictions and Guidelines
21264/EV68A Hardware Reference Manual
Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR
ALIGN_FETCH_BLOCK
sys__cbox:
mb ; quiet the dstream
hw_mfpr p6, EV6__I_CTL ; (4,0L) get i_ctl
lda p4, ^xFCFF(r31) ; mask for clearing SBE bits
and p6, p4, p4 ; clear SBE bits
sbe_off_offset = <sys__cbox_sbe_off_done - sys__cbox_sbe_off>
hw_mtpr p4, EV6__I_CTL ; (4,0L) write new i_ctl
br p6, sys__cbox_sbe_off
sys__cbox_sbe_off:
addq p6, #<sbe_off_offset+1>, p6 ; past stall in palmode
bsr r31, . ; stack push
ALIGN_FETCH_BLOCK <^x47FF041F>; align
hw_mtpr r31, EV6__IC_FLUSH ; (4,0L) eliminate prefetches
bne r31, . ; pvc #24
PVC_JSR sbe_off ; synch and flush
hw_ret_stall (p6) ; use ret, pop stack
PVC_JSR sbe_off, dest=1 ; br stops predictor
sys__cbox_sbe_off_done:
br r31, sys__cbox_touch1 ; now pull in the next block
ALIGN_CACHE_BLOCK
sys__cbox_over1: ; block 1
addq r31, #11, p6 ; initialize shift count (11x)
addq r31, r31, p7 ; initialize shift data
br r31, sys__cbox_over2 ; go to block 2
sys__cbox_touch1: ;
br r31, sys__cbox_touch2 ; touch block 2
sys__cbox_over2: ; block 2
hw_mtpr r31, EV6__SHIFT_CONTROL ; (6,0L) shift in 6 bits
subq p6, #1, p6 ; decrement shift count
br r31, sys__cbox_over3 ; go to block 3
sys__cbox_touch2: ;
br r31, sys__cbox_touch3 ; touch block 3
sys__cbox_over3: ; block 3
hw_mtpr r31, <EV6__MM_STAT ! 64 > ; (6,0L) wait for shift
bis p5, #1, p5 ; return in pal mode
br r31, sys__cbox_over4 ; go to block 4
sys__cbox_touch3: ;
br r31, sys__cbox_touch4 ; touch block 4
sys__cbox_over4: ; block 4
hw_mfpr p4, EV6__DATA ; (6,0L) read cbox data
bis r31, r31, r31 ; nop
br r31, sys__cbox_over5 ; go to block 5
sys__cbox_touch4: ;
br r31, sys__cbox_touch5 ; touch block 5
sys__cbox_over5: ; block 5
and p4, #^x3F, p4 ; clean to <5:0>
addq p4, p7, p7 ; accumulate shift data
br r31, sys__cbox_over6 ; go to block 6
sys__cbox_touch5: ;
br r31, sys__cbox_touch6 ; touch block 6