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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 105 Revision 1.4 (08-19-08)
DATASHEET
1588_CONFIG
45 1
1588_INT_STS_EN
45 1
MANUAL_FC_1
45 1
MANUAL_FC_2
45 1
MANUAL_FC_MII
45 1
SWITCH_CSR_DATA
45 1
SWITCH_CSR_CMD
45 1
E2P_CMD
45 1
E2P_DATA
45 1
LED_CFG
45 1
VPHY_BASIC_CTRL
45 1
VPHY_BASIC_STATUS
45 1
VPHY_ID_MSB
45 1
VPHY_ID_LSB
45 1
VPHY_AN_ADV
45 1
VPHY_AN_LP_BASE_ABILITY
45 1
VPHY_AN_EXP
45 1
VPHY_SPECIAL_CONTROL_STATUS
45 1
GPIO_CFG
45 1
GPIO_DATA_DIR
45 1
GPIO_INT_STS_EN
45 1
SWITCH_MAC_ADDRH
45 1
SWITCH_MAC_ADDRL
45 1
RESET_CTL
45 1
SWITCH_CSR_DIRECT_DATA
NA NA
Table 8.1 Read After Write Timing Rules (continued)
REGISTER NAME
MINIMUM WAIT TIME FOR
READ FOLLOWING ANY
WRITE CYCLE (IN NS)
NUMBER OF BYTE_TEST
READS
(ASSUMING T
CYC
OF 45NS)