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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 322 SMSC LAN9311/LAN9311i
DATASHEET
14.5.1.3 Switch Global Interrupt Mask Register (SW_IMR)
This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch
related interrupts in the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this
register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked switch fabric interrupt is generated in the Switch Global
Interrupt Pending Register (SW_IPR), the interrupt will trigger the SWITCH_INT bit in the Interrupt
Status Register (INT_STS). Refer to Chapter 5, "System Interrupts," on page 49 for more information.
Register #: 0004h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:9 RESERVED RO -
8:7
RESERVED
Note:
These bits must be written as 11b
R/W 11b
6
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of switch fabric interrupts due to the
Buffer Manager via the Buffer Manager Interrupt Pending Register
(BM_IPR). The status bits in the SW_IPR register are not affected.
R/W 1b
5
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of switch fabric interrupts due to the
Switch Engine via the Switch Engine Interrupt Pending Register (SWE_IPR).
The status bits in the SW_IPR register are not affected.
R/W 1b
4:3
RESERVED
Note: These bits must be written as 11b
R/W 11b
2
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of switch fabric interrupts due to the Port
2 MAC via the MAC_IPR_2 register (see Section 14.5.2.44, on page 367).
The status bits in the SW_IPR register are not affected.
R/W 1b
1
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of switch fabric interrupts due to the Port
1 MAC via the MAC_IPR_1 register (see Section 14.5.2.44, on page 367).
The status bits in the SW_IPR register are not affected.
R/W 1b
0
Port 0 MAC Interrupt Mask (MAC_MII)
When set, prevents the generation of switch fabric interrupts due to the Port
0 MAC via the MAC_IPR_MII register (see Section 14.5.2.44, on page 367).
The status bits in the SW_IPR register are not affected.
R/W 1b