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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 159 Revision 1.4 (08-19-08)
DATASHEET
11.2.2 PTP Message Detection
In order to provide the most flexibility, loose packet type matching is used by the LAN9311/LAN9311i.
This assumes that for all packets received with a valid FCS, only the MAC destination address is
required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in
the PTP protocol: 224.0.1.129 through 224.0.1.132. These map to Ethernet MAC addresses
01:00:5e:00:01:81 through 01:00:5e:00:01:84. Each of these addresses has one enable bit per port in
the 1588 Configuration Register (1588_CONFIG) which enables/disables the corresponding address
as a PTP address on the specified port.
In addition to the fixed addresses, a user defined (host programmable) PTP address may be input via
the 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) and 1588 Auxiliary MAC
Address Low-DWORD Register (1588_AUX_MAC_LO). The user defined address may be
disabled/enabled as a PTP address on each port via the dedicated enable bits in the 1588
Configuration Register (1588_CONFIG). A summary of the supported PTP multicast addresses and
corresponding enable bits can be seen in Table 11.3.
Once a packet is determined to match a PTP destination address, it is further qualified as a Sync or
Delay_Req message type. On Ethernet, PTP uses UDP messages. Within the UDP payload is the PTP
control byte (offset 32 starting at 0). This byte determines the message type: 0x00 for a Sync message,
0x01 for a Delay_Req message. The UDP payload starts at packet byte offset 42 (from 0) for untagged
packets and at byte offset 46 for tagged packets.
Note: Both tagged and untagged packets are supported. Only Ethernet II packet encoding and IPv4
are supported.
Note: For proper routing of the PTP packets, the host must program an entry into the switch engine
Address Logic Resolution (ALR) Table. The MAC address should be one of the reserved
Multicast addresses in Table 11.3, with Port 0(Host MAC) as a destination.The Static and Valid
bits must also be set. Refer to Chapter 6, "Switch Fabric," on page 55 for more information.
Table 11.3 PTP Multicast Addresses
PTP ADDRESS
CORRESPONDING
MAC ADDRESS
RELATED ENABLE BITS IN THE
1588_CONFIG REGISTER
224.0.1.129
(Primary)
01:00:5e:00:01:81 MAC_PRI_EN_1 (Port 1)
MAC_PRI_EN_2 (Port 2)
MAC_PRI_EN_MII (Port 0)
224.0.1.130
(Alternate 1)
01:00:5e:00:01:82 MAC_ALT1_EN_1 (Port 1)
MAC_ALT1_EN_2 (Port 2)
MAC_ALT1_EN_MII (Port 0)
224.0.1.131
(Alternate 2)
01:00:5e:00:01:83 MAC_ALT2_EN_1 (Port 1)
MAC_ALT2_EN_2 (Port 2)
MAC_ALT2_EN_MII (Port 0)
224.0.1.132
(Alternate 3)
01:00:5e:00:01:84 MAC_ALT3_EN_1 (Port 1)
MAC_ALT3_EN_2 (Port 2)
MAC_ALT3_EN_MII (Port 0)
User Defined User Defined Address
(1588_AUX_MAC_HI &
1588_AUX_MAC_LO registers)
MAC_USER_EN_1 (Port 1)
MAC_USER_EN_2 (Port 2)
MAC_USER_EN_MII (Port 0)