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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 325 Revision 1.4 (08-19-08)
DATASHEET
14.5.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
This read/write register configures the packet type passing parameters of the port.
Register #: Port0: 0401h Size: 32 bits
Port1: 0801h
Port2: 0C01h
BITS DESCRIPTION TYPE DEFAULT
31:8 RESERVED RO -
7
RESERVED
Note:
This bit must always be written as 0.
R/W 0b
6
RESERVED RO -
5
Enable Receive Own Transmit
When set, the switch port will receive its own transmission if it is looped back
from the PHY. Normally, this function is only used in Half Duplex PHY
loopback.
R/W 0b
4
RESERVED RO -
3
Jumbo2K
When set, the maximum packet size accepted is 2048 bytes. Statistics
boundaries are also adjusted.
R/W 0b
2
RESERVED RO -
1
Reject MAC Types
When set, MAC control frames (packets with a type field of 8808h) are
filtered. When cleared, MAC Control frames, other than MAC Control Pause
frames, are sent to the forwarding process. MAC Control Pause frames are
always consumed by the switch.
R/W 1b
0
RX Enable
When set, the receive port is enabled. When cleared, the receive port is
disabled.
R/W 1b