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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 204 SMSC LAN9311/LAN9311i
DATASHEET
14.2.5.3 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register
(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)
Note:
The selection between Sync or Delay_Req packets is based on the corresponding
master/slave bit in the 1588 Configuration Register (1588_CONFIG).
Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i.
Refer to Section 14.2.5 for additional information.
Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to
the switch fabric.
Offset: Port 1: 108h Size: 32 bits
Port 2: 128h
Port 0: 148h
BITS DESCRIPTION TYPE DEFAULT
31:16 Sequence ID (SEQ_ID)
This field contains the Sequence ID from the 1588 Sync or Delay_Req
packet.
RO 0000h
15:0
Source UUID High (SRC_UUID_HI)
This field contains the high 16-bits of the Source UUID from the 1588 Sync
or Delay_Req packet.
RO 0000h