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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 450 SMSC LAN9311/LAN9311i
DATASHEET
15.5.6 RX Data FIFO Direct PIO Read Cycle Timing
Please refer to Section 8.5.6, "RX Data FIFO Direct PIO Reads," on page 109 for a functional
description of this mode.
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle
ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing
Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Read Cycle Time 45 nS
t
csl
CS, nRD Assertion Time 32 nS
t
csh
nCS, nRD De-assertion Time 13 nS
t
csdv
nCS, nRD Valid to Data Valid 30 nS
t
asu
Address, FIFO_SEL Setup to nCS, nRD Valid 0 nS
t
ah
Address, FIFO_SEL Hold Time 0 nS
t
don
Data Buffer Turn On Time 0 nS
t
doff
Data Buffer Turn Off Time 9 nS
t
doh
Data Output Hold Time 0 nS
t
ah
A[x:1], END_SEL
nCS, nRD
D[15:0]
FIFO_SEL
t
asu
t
cycle
t
csl
t
csh
t
doff
t
csdv
t
don
t
doh