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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 98 SMSC LAN9311/LAN9311i
DATASHEET
(VPHY_BASIC_CTRL). The speed and duplex bits in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) should be ignored when auto-negotiation is enabled.
7.3.1.3 Virtual PHY Pause Flow Control
The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs
advertised pause flow control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric
Pause) of the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV). This allows the
Virtual PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the
emulated link partner. The default values of these bits are as shown in Section 14.2.8.5, "Virtual PHY
Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page 253.
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised
pause flow control abilities of the Virtual PHY in (bits 10 & 11) of the Virtual PHY Auto-Negotiation
Advertisement Register (VPHY_AN_ADV). Thus, the emulated link partner always accommodates the
asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in Table 14.5,
“Emulated Link Partner Pause Flow Control Ability Default Values,” on page 256.
The pause flow control settings may also be manually set via the Port 0(Host MAC) Manual Flow
Control Register (MANUAL_FC_MII). This register allows the switch fabric port 0 flow control settings
to be manually set when auto-negotiation is disabled or the Manual Flow Control Select bit 0 is set.
The currently enabled duplex and flow control settings can also be monitored via this register. The flow
control values in the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) are not
affected by the values of the manual flow control register. Refer to Section 6.2.3, "Flow Control Enable
Logic," on page 58 for additional information.
7.3.2 Virtual PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY
supports three block specific resets. These are is discussed in the following sections. For detailed
information on all LAN9311/LAN9311i resets, refer to Section 4.2, "Resets," on page 36.
7.3.2.1 Virtual PHY Software Reset via RESET_CTL
The Virtual PHY can be reset via the Reset Control Register (RESET_CTL) by setting bit 3
(VPHY_RST). This bit is self clearing after approximately 102uS.
7.3.2.2 Virtual PHY Software Reset via VPHY_BASIC_CTRL
The Virtual PHY can also be reset by setting bit 15 (VPHY_RST) of the Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL). This bit is self clearing and will return to 0 after the reset is complete.
7.3.2.3 Virtual PHY Software Reset via PMT_CTRL
The Virtual PHY can be reset via the Power Management Control Register (PMT_CTRL) by setting bit
10 (VPHY_RST). This bit is self clearing after approximately 102uS.