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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 260 SMSC LAN9311/LAN9311i
DATASHEET
14.2.9 Miscellaneous
This section details the remainder of the System CSR’s. These registers allow for monitoring and
configuration of various LAN9311/LAN9311i functions such as the Chip ID/revision, byte order testing,
power management, hardware configuration, general purpose timer, and free running counter.
14.2.9.1 Chip ID and Revision (ID_REV)
This read-only register contains the ID and Revision fields for the LAN9311/LAN9311i.
Note 14.46 Default value is dependent on device revision.
Offset: 050h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:16 Chip ID
This field indicates the chip ID.
RO 9311h
15:0
Chip Revision
This field indicates the design revision.
RO Note 14.46