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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 111 Revision 1.4 (08-19-08)
DATASHEET
8.5.8 PIO Writes
PIO writes are used for all LAN9311/LAN9311i write cycles. PIO writes can be performed using Chip
Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted.
The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control
signals must de-assert between cycles for the period specified in Table 15.12, “PIO Write Cycle Timing
Values,” on page 452. They may be asserted and de-asserted in any order. Either or both of these
control signals must be de-asserted between cycles for the period specified. The PIO write cycle is
illustrated in the functional timing diagram in Figure 8.7.
The END_SEL signal has the same timing characteristics as the address lines.
Please refer to Section 15.5.8, "PIO Write Cycle Timing," on page 452 for the AC timing specifications
for PIO write operations.
Figure 8.7 Functional Timing for PIO Write Operation
VALID
VALID
D[15:0] (INPUT)
nCS, nWR
A[x:1]
VALID
END_SEL