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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 384 SMSC LAN9311/LAN9311i
DATASHEET
14.5.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
This register indicates the current DIFFSERV command status.
Register #: 1814h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:1 RESERVED RO -
0
Operation Pending
When set, this bit indicates that the read or write command is taking place.
This bit is cleared once the command has finished.
RO
SC
0b