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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 219 Revision 1.4 (08-19-08)
DATASHEET
14.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)
This read/write register combined with 1588 Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO) form the 64-bit 1588 Clock Target Reload value. The 1588
Clock Target Reload is the value that is reloaded to the 1588 Clock Compare value when a clock
compare event occurs and the Reload/Add (RELOAD_ADD) bit of the 1588 Configuration Register
(1588_CONFIG) is set. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 155 for
additional information.
Note: Both this register and the 1588 Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO) must be written for either to be affected.
Offset: 184h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:0 Clock Target Reload High (CLOCK_TARGET_RELOAD_HI)
This field contains the high 32-bits of the 64-bit 1588 Clock Target Reload
value that is reloaded to the 1588 Clock Compare value.
R/W 00000000h