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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 453 Revision 1.4 (08-19-08)
DATASHEET
15.5.9 TX Data FIFO Direct PIO Write Cycle Timing
Please refer to Section 8.5.9, "TX Data FIFO Direct PIO Writes," on page 112 for a functional
description of this mode.
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Write Cycle Time 45 nS
t
csl
nCS, nWER Assertion Time 32 nS
t
csh
nCS, nWR De-assertion Time 13 nS
t
asu
Address, FIFO_SEL Setup to nCS, nWR Assertion 0 nS
t
ah
Address, FIFO_SEL Hold Time 0 nS
t
dsu
Data Setup to nCS, nWR De-assertion 7 nS
t
dh
Data Hold Time 0 nS
t
ah
t
dsu
A[2:1], END_SEL
nCS, nWR
D[15:0]
FIFO_SEL
t
dh
t
csh
t
cycle
t
csl
t
asu