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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 140 SMSC LAN9311/LAN9311i
DATASHEET
Figure 10.1 illustrates the process required to perform an EEPROM read or write operation.
10.2.2 I
2
C EEPROM
The I
2
C master implements a low level serial interface (start and stop condition generation, data bit
transmission and reception, acknowledge generation and reception) for connection to I
2
C EEPROMs,
and consists of a data wire (EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the
master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up
resistors.
The serial clock is also used as an input as it can be held low by the slave device in order to wait-
state the data cycle. Once the slave has data available or is ready to receive, it will release the clock.
Assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. In
the event that the slave device holds the clock low for more than 30mS, the current command
sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is
set. Both the clock and data signals have Schmitt trigger inputs and digital input filters. The digital filters
reject pulses that are less than 100nS.
Note: Since the I
2
C master is designed to access EEPROM only, multi-master arbitration is not
supported.
Based on the configuration strap eeprom_size_strap, various sized I
2
C EEPROMs are supported. The
varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the
EEPROM Command Register (E2P_CMD). Within each size range, the largest EEPROM uses all the
address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM
Figure 10.1 EEPROM Access Flow Diagram
EEPROM Write
Idle
Write
E2P_DATA
Register
Write
E2P_CMD
Register
Read
E2P_CMD
Register
EPC_BUSY = 0
EEPROM Read
Idle
Write
E2P_CMD
Register
Read
E2P_CMD
Register
Read
E2P_DATA
Register
EPC_BUSY = 0