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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 164 SMSC LAN9311/LAN9311i
DATASHEET
13.2.1 GPIO IEEE 1588 Timestamping
Two of the GPIO pins, GPIO[9:8], have the option to be used for IEEE 1588 time stamp functions. This
allows a time stamp capture to be triggered when the GPIO is configured as an input, or output a signal
from the GPIO based on an IEEE 1588 clock target compare event when configured as an output.
Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 155 for additional information
on the IEEE 1588 time stamping functions of the LAN9311/LAN9311i.
13.2.1.1 IEEE 1588 GPIO Inputs
When the GPIO[9:8] pins are configured as inputs, an active edge will capture the IEEE 1588 clock
into the high and low 1588 capture registers (1588_CLOCK_HI_CAPTURE_GPIO_x, and
1588_CLOCK_LO_CAPTURE_GPIO_x where “x” represents the number of the respective 1588
enabled GPIO) and set the corresponding interrupt flags GPIO[9:8]_INT and 1588_GPIO[9:8]_INT in
the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and 1588
Interrupt Status and Enable Register (1588_INT_STS_EN) respectively. The GPIO[9:8] inputs can also
be configured to clear the Clock Target interrupt (1588_TIMER_INT) in the 1588 Interrupt Status and
Enable Register (1588_INT_STS_EN) by setting the corresponding
GPIO_1588_TIMER_INT_CLEAR_EN[9:8] bit in the General Purpose I/O Configuration Register
(GPIO_CFG). GPIO inputs must be active for greater than 40nS to be recognized as capture or
interrupt clear events.
13.2.1.2 IEEE 1588 GPIO Outputs
The GPIO[9:8] pins can be configured as IEEE 1588 enabled outputs by setting the corresponding
1588_GPIO_OE[9:8] bits in the General Purpose I/O Configuration Register (GPIO_CFG). These bits
override the GPDIR[9:8] bits of the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)
and allow for GPIO output generation based on the IEEE 1588 clock target compare event. Clock
target compare events occur when the value loaded into the 1588 Clock Target High-DWORD Register
(1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD Register
(1588_CLOCK_TARGET_LO) matches the current IEEE 1588 clock value in the 1588 Clock High-
DWORD Register (1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO).
Upon detection of a clock target compare event, GPIO[9:8] can be configured to output a 100nS pulse,
toggle its output, or reflect the 1588_TIMER_INT bit in the 1588 Interrupt Status and Enable Register
(1588_INT_STS_EN) by enabling the GPIO_EVENT_9 or GPIO_EVENT_8 bits of the 1588
Configuration Register (1588_CONFIG). The clock event polarity, which determines whether the IEEE
1588 GPIO output is active high or active low, is controlled via the GPIO_EVENT_POL_9 and
GPIO_EVENT_POL_8 bits of the General Purpose I/O Configuration Register (GPIO_CFG).
Note: The 1588_GPIO_OE[9:8] bits do not override the GPIO buffer type bits GPIOBUF[9:8] in the
General Purpose I/O Configuration Register (GPIO_CFG).
13.2.2 GPIO Interrupts
Each GPIO of the LAN9311/LAN9311i provides the ability to trigger a unique GPIO interrupt in the
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). Reading the
GPIO_INT[11:0] bits of this register provides the current status of the corresponding interrupt, and each
interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit. The GPIO/LED Controller
aggregates the enabled interrupt values into an internal signal which is sent to the System Interrupt
Controller and is reflected via the Interrupt Status Register (INT_STS) bit 12 (GPIO). For more
information on the LAN9311/LAN9311i interrupts, refer to Chapter 5, "System Interrupts," on page 49.
13.2.2.1 GPIO Interrupt Polarity
The interrupt polarity can be set for each individual GPIO via the GPIO_INT_POL[11:0] bits in the
General Purpose I/O Configuration Register (GPIO_CFG). When set, a high logic level on the GPIO
pin will set the corresponding interrupt bit in the General Purpose I/O Interrupt Status and Enable
Register (GPIO_INT_STS_EN). When cleared, a low logic level on the GPIO pin will set the
corresponding interrupt bit. Because GPIO[9:8] have added IEEE 1588 functionality, the