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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 241 Revision 1.4 (08-19-08)
DATASHEET
14.2.6.8 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
This write-only register set is used to perform directly addressed write operations to the Switch Fabric
CSR’s. Using this set of registers, writes can be directly addressed to select Switch Fabric registers,
as specified in Table 14.3.
Writes within the Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
address range automatically set the appropriate address, set the four byte enable bits, clear the R/nW
bit and set the Busy bit in the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD).
The completion of the write cycle is indicated when the Busy bit is cleared. The address that is set in
the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) is mapped via Table 14.3.
For more information on this method of writing to the Switch Fabric CSR’s, refer to Section 6.2.3, "Flow
Control Enable Logic," on page 58.
Note: This set of registers is for write operations only. Reads can be performed via the Switch Fabric
CSR Interface Command Register (SWITCH_CSR_CMD) and Switch Fabric CSR Interface
Data Register (SWITCH_CSR_DATA) registers only.
Offset: 200h - 2DCh Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:0 Switch CSR Data (CSR_DATA)
This field contains the value to be written to the corresponding Switch Fabric
register.
WO 00000000h
Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map
REGISTER NAME
SWITCH FABRIC CSR
REGISTER #
SWITCH_CSR_DIRECT_DATA
ADDRESS
General Switch CSRs
SW_RESET 0001h 200h
SW_IMR 0004h 204h
Switch Port 0 CSRs
MAC_RX_CFG_MII 0401h 208h
MAC_TX_CFG_MII 0440h 20Ch
MAC_TX_FC_SETTINGS_MII
0441h 210h
MAC_IMR_MII 0480h 214h
Switch Port 1 CSRs
MAC_RX_CFG_1 0801h 218h
MAC_TX_CFG_1 0840h 21Ch
MAC_TX_FC_SETTINGS_1 0841h 220h
MAC_IMR_1 0880h 224h
Switch Port 2 CSRs
MAC_RX_CFG_2 0C01h 228h