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116 AMD Geode™ SC3200 Processor Data Book
SuperI/O Module
32581C
Table 5-29. Banks 0 and 1 - Common Control and Status Registers
Bit Description
Offset 00h Wakeup Events Status Register - WKSR (R/W1C) Reset Value: 00h
This register is set to 00h on power-up of V
PP
or software reset. It indicates which wakeup event and/or PME occurred. (See Section
6.2.9.4 "Power Management Events" on page 158.)
7 Reserved.
6 Reserved. Must be set to 0.
5 IRRX1 (CEIR) Event Status. This sticky bit shows the status of the CEIR event detection.
0: Event not detected. (Default)
1: Event detected.
4:2 Reserved.
1 RI2# Event Status. This sticky bit shows the status of RI2# event detection.
0: Event not detected. (Default)
1: Event detected.
0 SDATA_IN2 Event Status. This sticky bit shows the status of Audio Codec event detection.
0: Event not detected. (Default)
1: Event detected.
Offset 01h Wakeup Events Control Register - WKCR (R/W) Reset Value: 03h
This register is set to 03h on power-up of V
PP
or software reset. Detected wakeup events that are enabled issue a power-up request the
ACPI controller and/or a PME to the Core Logic module. (See Section 6.2.9.4 "Power Management Events" on page 158.)
7 Reserved.
6 Reserved. Must be set to 0.
5 IRRX1 (CEIR) Event Enable.
0: Disable. (Default)
1: Enable.
4:2 Reserved.
1 RI2# Event Enable.
0: Disable.
1: Enable. (Default)
0 SDATA_IN2 Event Enable.
0: Disable.
1: Enable. (Default)
Offset 02h Wakeup Configuration Register - WKCFG (R/W) Reset Value: 00h
This register is set to 00h on power-up of V
PP
or software reset. It enables access to CEIR registers.
7:5 Reserved.
4 Reserved. Must be set to 0.
3 Reserved. Must be set to 0.
2 Reserved.
1:0 Configuration Bank Select Bits.
00: Only shared registers are accessible.
01: Shared registers and Bank 1 (CEIR) registers are accessible.
10: Bank selected.
11: Reserved.