AMD SC3200 Computer Hardware User Manual


 
14 AMD Geode™ SC3200 Processor Data Book
Overview
32581C
1.2 Features
General Features
32-Bit x86 processor, up to 266 MHz, with MMX instruc-
tion set support
Memory controller with 64-bit SDRAM interface
2D graphics accelerator
CCIR-656 video input port with direct video for full
screen display
PC/AT functionality
PCI bus controller
IDE interface, two channels
USB, three ports, OHCI (OpenHost Controller Interface)
version 1.0 compliant
Audio, AC97/AMC97 version 2.0 compliant
Virtual System Architecture (VSA) technology support
Power management, ACPI (Advanced Configuration
Power Interface) version 1.0 compliant
Package:
BGU481 (481-Terminal Ball Grid Array Cavity Up)
GX1 Processor Module
CPU Core:
32-Bit x86, 266 MHz, with MMX compatible instruc-
tion set support
16 KB unified L1 cache
Integrated FPU (Floating Point Unit)
Re-entrant SMM (System Management Mode)
enhanced for VSA
2D Graphics Accelerator:
Accelerates BitBLTs, line draw and text
Supports all 256 raster operations
Supports transparent BLTs
Runs at core clock frequency
Memory Controller:
64-Bit SDRAM interface
66 MHz to 100 MHz frequency range
Direct interface with CPU/cache, display controller
and 2D graphic accelerator
Supports clock suspend and power-down/
self-refresh
Up to two banks of SDRAM (8 devices total) or one
SODIMM
Display Controller:
Hardware graphics frame buffer compress/
decompress
Hardware cursor, 32x32 pixels
Video Processor Module
Video Accelerator:
Flexible video scaling support of up to 800%
(horizontally and vertically)
Bilinear interpolation filters (with two taps, and eight
phases) to smooth output video
Video/Graphics Mixer:
8-bit value alpha blending
Three blending windows with constant alpha value
Color key
Video Input Port (VIP):
Video capture or display
CCIR-656 and VESA Video Interface Port v1.1
compliant
Lock display timing to video input timing (GenLock)
Able to transfer video data into main memory
Direct video transfer for full screen display
Separate memory location for VBI
TFT Interface:
Direct connection to TFT panels
800x600 non-interlaced TFT @ 16 bpp graphics,
up to 85 Hz
1024x768 non-interlaced TFT @ 16 bpp graphics,
up to 75 Hz
TFT on IDE: FPCLK max is 40 MHz
TFT on Parallel Port: FPCLK max is 80 MHz
Core Logic Module
Audio Codec Interface:
AC97/AMC97 (Rev. 2.0) codec interface
Six DMA channels
PC/AT Functionality:
Programmable Interrupt Controller (PIC),
8259A-equivalent
Programmable Interval Timer (PIT), 8254-equivalent
DMA Controller (DMAC), 8237-equivalent
Power Management:
ACPI v1.0 compliant
Sx state control of three power planes
Cx/Sx state control of clocks and PLLs
Thermal event input
Wakeup event support:
Three general-purpose events
AC97 codec event
UART2 RI# signal
Infrared (IR) event
General Purpose I/Os (GPIOs):
27 multiplexed GPIO signals
Low Pin Count (LPC) Bus Interface:
Specification v1.0 compatible