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AMD Geode™ SC3200 Processor Data Book 59
Signal Definitions
32581C
IDE_IORDY0 AD1 I I/O Ready Channels 0 and 1. When de-asserted, these
signals extend the transfer cycle of any host register
access if the required device is not ready to respond to
the data transfer request.
Note: If selected as IDE_IORDY0 or IDE_IORDY1
function(s) but not used, then signal(s) should be
tied high.
TFTD11
IDE_IORDY1 B29 I GPIO10+DSR2#+
SDTEST1
IDE_DREQ0 AC4 I DMA Request Channels 0 and 1. The IDE_DREQ sig-
nals are used to request a DMA transfer from the
SC3200. The direction of transfer is determined by the
IDE_IOR/IOW signals.
Note: If selected as IDE_DREQ0/ IDE_DREQ1 func-
tion but not used, tie IDE_DREQ0/IDE_DREQ1
low.
TFTD8
IDE_DREQ1 C31 I GPIO8+CTS2#
+SDTEST5
IDE_DACK0# AD4 O DMA Acknowledge Channels 0 and 1. The
IDE_DACK# signals acknowledge the DREQ request to
initiate DMA transfers.
TFTD0
IDE_DACK1# C30 O GPIO7+RTS2#
+SDTEST0
IRQ14 AF1 I Interrupt Request Channels 0 and 1. These input sig-
nals are edge-sensitive interrupts that indicate when the
IDE device is requesting a CPU interrupt service.
Note: If selected as IRQ14/IRQ15 function but not
used, tie IRQ14/IRQ15 low.
TFTD1
IRQ15 AJ8 I GPIO11+RI2#
3.4.9 IDE Interface Signals (Continued)
Signal Name Ball No. Type Description Mux
3.4.10 Universal Serial Bus (USB) Interface Signals
Signal Name Ball No. Type Description Mux
POWER_EN AH1 O Power Enable. This signal enables the power to a self-
powered USB hub.
---
OVER_CUR# AF4 I Overcurrent. This signal indicates that the USB hub has
detected an overcurrent on the USB.
---
DPOS_PORT1 A28 I/O
USB Port 1 Data Positive for Port 1.
1
---
DNEG_PORT1 A29 I/O
USB Port 1 Data Negative for port 1.
1
---
DPOS_PORT2 B27 I/O
USB Port 2 Data Positive for Port 2.
1
---
DNEG_PORT2 B28 I/O
USB Port 2 Data Negative for Port 2.
1
---
DPOS_PORT3 A26 I/O
USB Port 3 Data Positive for Port 3.
1
---
DNEG_PORT3 A27 I/O
USB Port 3 Data Negative for Port 3.
1
---
1. A 15K ohm pull-down resistor is required on all ports (even if unused).