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34 AMD Geode™ SC3200 Processor Data Book
Signal Definitions
32581C
L29 GPIO35 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD3 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
L30 GPIO34 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD2 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
L31 GPIO33 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD1 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
M1 V
SS
GND --- --- ---
M2 AD7 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A7 O O
PCI
M3 V
IO
PWR --- --- ---
M4 AD8 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A8 O O
PCI
M28 GPIO32 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD0 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
M29 GPIO13 I/O
(PU
22.5
)
IN
AB
,
O
8/8
V
IO
PMR[19] = 0
AB2D I/O
(PU
22.5
)
IN
AB
,
OD
8
V
IO
PMR[19] = 1
M30 V
IO
PWR --- --- ---
M31 V
SS
GND --- --- ---
N1 AD3 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A3 O O
PCI
N2 AD6 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A6 O O
PCI
N3 AD5 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A5 O O
PCI
N4 V
SS
GND --- --- ---
N13 V
CORE
PWR --- --- ---
N14 V
CORE
PWR --- --- ---
N15 V
SS
GND --- --- ---
N16 V
SS
GND --- --- ---
N17 V
SS
GND --- --- ---
N18 V
CORE
PWR --- --- ---
N19 V
CORE
PWR --- --- ---
N28 V
SS
GND --- --- ---
Ball
No. Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail Configuration
N29 GPIO12 I/O
(PU
22.5
)
IN
AB
,
O
8/8
V
IO
PMR[19] = 0
AB2C I/O
(PU
22.5
)
IN
AB
,
OD
8
PMR[19] = 1
N30 AB1D I/O
(PU
22.5
)
IN
AB
,
OD
8
V
IO
PMR[23]
3
= 0
GPIO1 I/O
(PU
22.5
)
IN
T
,
O
3/5
PMR[23]
3
= 1 and
PMR[13] = 0
IOCS1# O O
3/5
PMR[23]
3
= 1 and
PMR[13] = 1
N31 AB1C I/O
(PU
22.5
)
IN
AB
,
OD
8
V
IO
PMR[23]
3
= 0
GPIO20 I/O
(PU
22.5
)
IN
T
,
O
3/5
PMR[23]
3
= 1 and
PMR[7] = 0
DOCCS# O O
3/5
PMR[23]
3
= 1 and
PMR[7] = 1
P1 AD4 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A4 O O
PCI
P2 IDE_CS1# O O
1/4
V
IO
PMR[24] = 0
TFTDE O O
1/4
PMR[24] = 1
P3 AD1 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A1 O O
PCI
P4 V
CORE
PWR --- --- ---
P13 V
CORE
PWR --- --- ---
P14 V
CORE
PWR --- --- ---
P15 V
SS
GND --- --- ---
P16 V
SS
GND --- --- ---
P17 V
SS
GND --- --- ---
P18 V
CORE
PWR --- --- ---
P19 V
CORE
PWR --- --- ---
P28 V
CORE
PWR --- --- ---
P29 SDATA_OUT O O
AC97
V
IO
---
TFT_PRSNT I
(PD
100
)
IN
STRP
V
IO
Strap (See Table 3-
4 on page 44.)
P30 SYNC O O
AC97
V
IO
---
CLKSEL3 I
(PD
100
)
IN
STRP
Strap (See Table 3-
4 on page 44.)
P31 AC97_CLK O O
2/5
V
IO
PMR[25] = 1
R1 V
SS
GND --- --- ---
R2 V
SS
GND --- --- ---
R3 V
SS
GND --- --- ---
R4 V
SS
GND --- --- ---
R13 V
SS
GND --- --- ---
R14 V
SS
GND --- --- ---
R15 V
SS
GND --- --- ---
R16 V
SS
GND --- --- ---
Ball
No. Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail Configuration
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)