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176 AMD Geode™ SC3200 Processor Data Book
Core Logic Module - Register Summary
32581C
B8h 8 RO DMA Shadow Register xxh Page 215
B9h 8 RO PIC Shadow Register xxh Page 215
BAh 8 RO PIT Shadow Register xxh Page 215
BBh 8 RO RTC Index Shadow Register xxh Page 216
BCh 8 R/W Clock Stop Control Register 00h Page 216
BDh-BFh --- --- Reserved 00h Page 216
C0h-C3h 32 R/W User Defined Device 1 Base Address Register 00000000h Page 216
C4h-C7h 32 R/W User Defined Device 2 Base Address Register 00000000h Page 216
C8h-CBh 32 R/W User Defined Device 3 Base Address Register 00000000h Page 216
CCh 8 R/W User Defined Device 1 Control Register 00h Page 217
CDh 8 R/W User Defined Device 2 Control Register 00h Page 217
CEh 8 R/W User Defined Device 3 Control Register 00h Page 217
CFh --- --- Reserved 00h Page 217
D0h 8 WO Software SMI Register 00h Page 217
D1h-EBh 16 --- Reserved 00h Page 217
ECh 8 R/W Timer Test Register 00h Page 218
EDh-F3h --- --- Reserved 00h Page 218
F4h 8 RC Second Level PME/SMI Status Register 1 00h Page 218
F5h 8 RC Second Level PME/SMI Status Register 2 00h Page 218
F6h 8 RC Second Level PME/SMI Status Register 3 00h Page 219
F7h 8 RC Second Level PME/SMI Status Register 4 00h Page 220
F8h-FFh --- --- Reserved 00h Page 221
Table 6-14. F0: PCI Header/Bridge Configuration Registers
for GPIO and LPC Support Summary (Continued)
F0 Index
Width
(Bits) Type Name
Reset
Value
Reference
(Table 6-29)