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AMD Geode™ SC3200 Processor Data Book 139
6
Core Logic Module 32581C
6.0Core Logic Module
The Core Logic module is an enhanced PCI-to-Sub-ISA
bridge (South Bridge), this module is ACPI-compliant, and
provides AT/Sub-ISA functionality. The Core Logic module
also contains state-of-the-art power management. Two bus
mastering IDE controllers are included for support of up to
four ATA-compliant devices. A three-port Universal Serial
Bus (USB) provides high speed, and Plug & Play expan-
sion for a variety of new consumer peripheral devices.
6.1 Feature List
Internal Fast-PCI Interface
The internal Fast-PCI bus interface is used to connect the
Core Logic and GX1 modules of the SC3200. This inter-
face includes the following features:
• PCI protocol for transfers on Fast-PCI bus
• Up to 66 MHz operation
• Subtractive decode handled internally in conjunction
with external PCI bus
Bus Mastering IDE Controllers
• Two controllers with support for up to four IDE devices
• Independent timing for master and slave devices for both
channels
• PCI bus master burst reads and writes
• Multiword DMA support
• Programmed I/O (PIO) Modes 0-4 support
Universal Serial Bus
• Three independent USB interfaces
• Open Host Controller Interface (OpenHCI) specification
compliant
PCI Interface
• PCI 2.1 compliant
• PCI master for AC97 and IDE controllers
• Subtractive agent for unclaimed transactions
• Supports PCI initiator-to-Sub-ISA cycle translations
• PCI-to-Sub-ISA interrupt mapper/translator
• External PCI bus
— Devices internal to the Core Logic module (IDE,
Audio, USB, Sub-ISA, etc.) cannot master to memory
through the external PCI bus.
— Legacy DMA is not supported to memory located on
external PCI bus.
— The Core Logic module does not transfer subtrac-
tively decoded I/O cycles originating from the
external PCI bus.
AT Compatibility
• 8259A-equivalent interrupt controllers
• 8254-equivalent timer
• 8237-equivalent DMA controllers
• Port A, B, and NMI logic
• Positive decode for AT I/O space
Sub-ISA Interface
• Boot ROM chip select
• Extended ROM to 16 MB
• Two general-purpose chip selects
• NAND Flash support
• M-Systems DiskOnChip support
• Is not the subtractive decode agent
Power Management
• Automated CPU 0V Suspend modulation
• I/O Traps and Idle Timers for peripheral power manage-
ment
• Software SMI and Stop Clock for APM support
• ACPI-compliant timer and register set
• Up to 22 GPIOs of which all can generate Power
Management Interrupts (PMEs)
• Three Dedicated GPWIOs powered by V
SBL
and V
SB
• Shadow register support for legacy controllers for 0V
Suspend