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AMD Geode™ SC3200 Processor Data Book 367
Electrical Specifications
32581C
9.3.3 TFT Interface
Figure 9-7. TFT Timing Diagram
Table 9-14. TFT Timing Parameters
Symbol Parameter Min Max Unit Comments
t
OV
TFTD[17:0], TFTDE valid time after
TFTDCK rising edge (multiplexed on IDE)
08ns
t
OV
TFTD[17:0], TFTDE valid time after
TFTDCK rising edge (multiplexed on
Parallel Port)
04ns
t
CLK_RF
TFTDCK rise/fall time
between 0.8V and
2.0V
3 ns Note 1
t
CLK_P
TFTDCK period time (multiplexed on IDE) 25 ns
t
CLK_P
TFTDCK period time (multiplexed on
Parallel Port)
12.5 ns
t
CLK_D
TFTDCK duty cycle 40/60 %
Note 1. Guaranteed by characterization
t
OV
t
CLK_RF
t
CLK_P
TFTDCK
TFTD[17:0]
TFTDE