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AMD Geode™ SC3200 Processor Data Book 237
Core Logic Module - SMI Status and ACPI Registers - Function 1
32581C
12 SMI Source is NMI. (Read to Clear) Indicates whether or not an SMI was caused by NMI activity.
0: No.
1: Yes.
11 SMI Source is IRQ2 of SIO Module. (Read to Clear) Indicates whether or not an SMI was caused by IRQ2 of the SIO
module.
0: No.
1: Yes.
The next level (second level) of SMI status is reported in the SuperI/O module. See Table 5-29 "Banks 0 and 1 - Common
Control and Status Registers" on page 116 for details.
10 SMI Source is EXT_SMI[7:0]. (Read Only. Read Does Not Clear) Indicates whether or not an SMI was caused by a neg-
ative-edge event on EXT_SMI[7:0].
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 24h[23:8].
9 SMI Source is General Timers/Traps. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused
by the expiration of one of the General Purpose Timers or one of the User Defined Traps.
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 04h/06h.
8 SMI Source is Software Generated. (Read to Clear) Indicates whether or not an SMI was caused by software.
0: No.
1: Yes.
7 SMI on an A20M# Toggle. (Read to Clear) Indicates whether or not an SMI was caused by an access to either Port 92h or
the keyboard command which initiates an A20M# SMI
0: No.
1: Yes.
This method of controlling the internal A20M# in the GX1 module is used instead of a pin.
To enable SMI generation, set F0 Index 53h[0] to 1.
6 SMI Source is a VGA Timer Event. (Read to Clear) Indicates whether or not an SMI was caused by expiration of the VGA
Timer (F0 Index 8Eh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[3] to 1.
5 SMI Source is Video Retrace. (Read to Clear) Indicates whether or not an SMI was caused by a video retrace event as
decoded from the internal serial connection (PSERIAL register, bit 7) from the GX1 module.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[2] to 1.
4 Reserved. Reads as 0.
3 SMI Source is LPC. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by the LPC inter-
face.
0: No.
1: Yes.
The next level (second level) of SMI status is at F0BAR1+I/O Offset 1Ch[6:5].
2 SMI Source is ACPI. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by an access (read
or write) to one of the ACPI registers (F1BAR1).
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 20h.
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit Description