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AMD Geode™ SC3200 Processor Data Book 177
Core Logic Module - Register Summary
32581C
Table 6-15. F0BAR0: GPIO Support Registers Summary
F0BAR0+
I/O Offset
Width
(Bits) Type Name
Reset
Value
Reference
(Table 6-30)
00h-03h 32 R/W GPDO0 — GPIO Data Out 0 Register FFFFFFFFh Page 222
04h-07h 32 RO GPDI0 — GPIO Data In 0 Register FFFFFFFFh Page 222
08h-0Bh 32 R/W GPIEN0 — GPIO Interrupt Enable 0 Register 00000000h Page 222
0Ch-0Fh 32 R/W1C GPST0 — GPIO Status 0 Register 00000000h Page 222
10h-13h 32 R/W GPDO1 — GPIO Data Out 1 Register FFFFFFFFh Page 223
14h-17h 32 RO GPDI1 — GPIO Data In 1 Register FFFFFFFFh Page 223
18h-1Bh 32 R/W GPIEN1 — GPIO Interrupt Enable 1 Register 00000000h Page 223
1Ch-1Fh 32 R/W1C GPST1 — GPIO Status 1 Register 00000000h Page 223
20h-23h 32 R/W GPIO Signal Configuration Select Register 00000000h Page 223
24h-27h 32 R/W GPIO Signal Configuration Access Register 00000044h Page 224
28h-2Bh 32 R/W GPIO Reset Control Register 00000000h Page 225
Table 6-16. F0BAR1: LPC Support Registers Summary
F0BAR1+
I/O Offset
Width
(Bits) Type Name
Reset
Value
Reference
(Table 6-31)
00h-03h 32 R/W SERIRQ_SRC — Serial IRQ Source Register 00000000h Page 226
04h-07h 32 R/W SERIRQ_LVL — Serial IRQ Level Control Register 00000000h Page 227
08h-0Bh 32 R/W SERIRQ_CNT — Serial IRQ Control Register 00000000h Page 229
0Ch-0Fh 32 R/W DRQ_SRC — DRQ Source Register 00000000h Page 229
10h-13h 32 R/W LAD_EN — LPC Address Enable Register 00000000h Page 230
14h-17h 32 R/W LAD_D0 — LPC Address Decode 0 Register 00080020h Page 231
18h-1Bh 32 R/W LAD_D1 — LPC Address Decode 1 Register 00000000h Page 232
1Ch-1Fh 32 R/W LPC_ERR_SMI — LPC Error SMI Register 00000080h Page 232
20h-23h 32 RO LPC_ERR_ADD — LPC Error Address Register 00000000h Page 233